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63096ha (ot)/n1594th (ot) b8-1326, 1328 no.4828-1/16 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 lc75852e lc75852w overview the lc75852e and lc75852w are 1/2 duty dynamic lcd display drivers. in addition to being able to directly drive lcd panels with up to 90 segments, they can also control up to four general-purpose output ports. these products also include a key scan circ uit which allows them to accept input from keypads with up to 30 keys. this allows end product front panel wiring to be simplified. features ? up to 30 key inputs (key scan is only performed when a key is pressed.) ? 1/2 duty ? 1/2 bias (up to 90 segments) ? sleep mode and the all segments off function can be controlled from serial data. ? segment output port/general-purpose output port usage can be controlled from serial data. ? serial data i/o supports ccb format co mmunication with the system controller. ? high generality since display data is displayed directly without decoder intervention ? reset pin that can establish the initial state. specifications absolute maximum ratings at ta = 25 ? c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ? 0.3 to +7.0 v input voltage v in osc, ce, cl, di, res , ki1 to ki5 ? 0.3 to v dd +0.3 v output voltage v out osc, do, s1 to s45, com1, com2, ks1 to ks6, p1 to p4 ? 0.3 to v dd +0.3 v output current i out 1 s1 to s45 100 ? a i out 2 com1, com2, ks1 to ks6 1 ma i out 3 p1 to p4 5 allowable power dissipation pd max ta = 85 ? c 200 mw operating temperature topr ? 40 to +85 ? c storage temperature tstg ? 55 to +125 ? c package dimensions unit : mm (typ) [ lc75852e ] [ lc75852w ] qip64e(14x14) sqfp64(10x10) cmos lsi asynchronous silicon gate 1/2 duty lcd driver with on-chip key input function ordering number : EN4828a ? ccb is a registered trademark of semiconductor components industries, llc. ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (1.25) 116 17 32 33 48 49 64
allowable operating ranges at ta = ?0 to +85 c, v ss = 0 v note: * since do is an open-drain output, these values differ depending on the pull-up resistor r pu and the load capacitance c l . electrical characteristics in the allowable operating ranges no. 4828- 2 /16 lc75852e, 75852w parameter symbol conditions min typ max unit supply voltage v dd v dd 4.5 6.0 v input high-level voltage v ih 1 ce, cl, di, res 0.8 v dd v dd v v ih 2 ki1 to ki5 0.6 v dd v dd v input low-level voltage v il ce, cl, di, res, ki1 to ki5 0 0.2 v dd v recommended external r osc osc 62 k resistance recommended external c osc osc 680 pf capacitance guaranteed oscillator range f osc osc 25 50 100 khz data setup time t ds cl, di: figure 1 160 ns data hold time t dh cl, di: figure 1 160 ns ce wait time t cp ce, cl: figure 1 160 ns ce setup time t cs ce, cl: figure 1 160 ns ce hold time t ch ce, cl: figure 1 160 ns high-level clock pulse width t ? cl: figure 1 160 ns low-level clock pulse width t ? cl: figure 1 160 ns rise time t r ce, cl, di: figure 1 160 ns fall time t f ce, cl, di: figure 1 160 ns do output delay time t dc do, r pu = 4.7 k , c l = 10 pf * : figure 1 1.5 s do rise time t dr do, r pu = 4.7 k , c l = 10 pf * : figure 1 1.5 s res switching time t2 figure 2 10 s parameter symbol conditions min typ max unit hysteresis v h ce, cl, di, res, ki1 to ki5 0.1 v dd v input high-level current i ih ce, cl, di, res: v i = 6.0 v 5.0 a input low-level current i il ce, cl, di, res: v i = 0 v ?.0 a input floating voltage v if ki1 to ki5 0.05 v dd v pull-down resistance r pd ki1 to ki5: v dd = 5.0 v 50 100 250 k output off leakage current i offh do: v o = 6.0 v 6.0 a v oh 1 ks1 to ks6: i o = ? ma v dd ?1.0 v output high-level voltage v oh 2 p1 to p4: i o = ? ma v dd ?1.0 v v oh 3 s1 to s45: i o = ?0 a v dd ?1.0 v v oh 4 com1, com2: i o = ?00 a v dd ?0.6 v v ol 1 ks1 to ks6: i o = 50 a 0.4 1.0 3.0 v v ol 2 p1 to p4: i o = 1 ma 1.0 v output low-level voltage v ol 3 s1 to s45: i o = 10 a 1.0 v v ol 4 com1, com2: i o = 100 a 0.6 v v ol 5 do: i o = 1 ma 0.1 0.5 v output middle-level voltage v mid 1 com1, com2: v dd = 6.0 v, i o = 100 a 2.4 3.0 3.6 v v mid 2 com1, com2: v dd = 4.5 v, i o = 100 a 1.65 2.25 2.85 v current drain i dd 1 sleep mode, ta = 25 c 5 a i dd 2 v dd = 6.0 v, output open, ta = 25 c, f osc = 50 khz 1.4 2.5 ma
1. when stopped with cl at the low level 2. when stopped with cl at the high level figure 1 pin assignment no. 4828- 3 /16 lc75852e, 75852w
block diagram pin functions no. 4828- 4 /16 lc75852e, 75852w pin pin no. function active i/o handling when unused s1/p1 to s4/p4 s5 to s43 com1 com2 ks1/s44, ks2/s45, ks3 to ks6 ki1 to ki5 osc ce cl di do res v dd v ss 1 to 4 5 to 43 44 45 46 47 48 to 51 52 to 56 57 62 63 64 61 59 60 58 segment outputs: used to output the display data that is transmitted over the serial data input. pins s1/p1 to s4/p4 can be used as general-purpose outputs according to control data specification. common driver outputs. the frame frequency f o is (f osc /512) hz. key scan outputs. when a key matrix is formed, normally a diode will be attached to the key scan timing line to prevent shorts. however, since the output transistor impedance is an unbalanced cmos output, it will not be damaged if shorted. pins ks1/s44 and ks2/s45 can be used as segment outputs according to control data specification. key scan inputs: pins with a built-in pull-down resistor. oscillator connection: oscillator circuit can be formed by connecting the pin to a resistor and a capacitor. ce: chip enable cl: synchronization clock di: transfer data do: output data serial data interface: connected to the controller. since do is an open-drain output, it requires a pull-up resistor. reset input that re-initializes the lsi internal states. during a reset, the display segments are turned off forcibly regardless of the internal display data. all internal key data is reset to low and the key scan operation is disabled. however, serial data can be input during a reset. power supply connection. a supply voltage of between 4.5 and 6.0 v must be provided. power supply ground connection. must be connected to gnd. h h l o o o i i/o i i i o i open open open gnd v dd gnd open gnd
serial data input 1. when stopped with cl at the low level 2. when stopped with cl at the high level ccb address ...................... [42h] d1 to d90 ........................... display data s0, s1 ................................ sleep control data k0, k1 ................................ key scan output/segment output selection data p0, p1 ................................ segment output port/general-purpose output port selection data sc ...................................... segment on/off control data no. 4828- 5 /16 lc75852e, 75852w
control data functions 1. s0, s1 ................. sleep control data this control data switches the lsi between normal mode and sleep mode. it also sets the key scan output standby states for pins ks1 to ks6. note: the ks1/s44 and ks2/s45 output pins are set to the key scan output state. 2. k0, k1 ................ key scan output/segment output selection data this control data switches the ks1/s44 and ks2/s45 output pins between the key scan output and segment output functions. x: don? care 3. p0, p1 ................. segment output port/general-purpose output port selection data this control data switches the s1/p1 to s4/p4 output pins between the segment output port and the general-purpose output port functions. the table below lists the correspondence between the display data and the output pins when the general-purpose output port function is selected. for example, if the output pin s4/p4 is set for use as a general-purpose output port, the output pin s4/p4 will output a high level when the display data d7 is 1. 4. sc ....................... segment on/off control data this control data controls the segment on/off states. no. 4828- 6 /16 lc75852e, 75852w control data mode oscillator segment outputs key scan standby mode output pin states s0 s1 common outputs ks1 ks2 ks3 ks4 ks5 ks6 0 0 normal oscillator operation h h h h h h 0 1 sleep stopped l l l l l l h 1 0 sleep stopped l l l l l h h 1 1 sleep stopped l h h h h h h control data output pin states maximum number k0 k1 ks1/s44 ks2/s45 of key inputs 0 0 ks1 ks2 30 0 1 s44 ks2 25 1 x s44 s45 20 control data output pin states p0 p1 s1/p1 s2/p2 s3/p3 s4/p4 0 0 s1 s2 s3 s4 0 1 p1 p2 s3 s4 1 0 p1 p2 p3 s4 1 1 p1 p2 p3 p4 output corresponding pin display data s1/p1 d1 s2/p2 d3 s3/p3 d5 s4/p4 d7 sc display state 0 on 1 off
display data and output pin correspondences for example, the output states of output pin s11 are listed in the table below. no. 4828- 7 /16 lc75852e, 75852w output pin com1 com2 s1/p1 d1 d2 s2/p2 d3 d4 s3/p3 d5 d6 s4/p4 d7 d8 s5 d9 d10 s6 d11 d12 s7 d13 d14 s8 d15 d16 s9 d17 d18 s10 d19 d20 s11 d21 d22 s12 d23 d24 s13 d25 d26 s14 d27 d28 s15 d29 d30 s16 d31 d32 s17 d33 d34 s18 d35 d36 s19 d37 d38 s20 d39 d40 s21 d41 d42 s22 d43 d44 s23 d45 d46 s24 d47 d48 s25 d49 d50 s26 d51 d52 s27 d53 d54 s28 d55 d56 s29 d57 d58 s30 d59 d60 s31 d61 d62 s32 d63 d64 s33 d65 d66 s34 d67 d68 s35 d69 d70 s36 d71 d72 s37 d73 d74 s38 d75 d76 s39 d77 d78 s40 d79 d80 s41 d81 d82 s42 d83 d84 s43 d85 d86 ks1/s44 d87 d88 ks2/s45 d89 d90 display data output pin state d21 d22 s11 0 0 segment off for both com1 and com2 0 1 segment on for com2 1 0 segment on for com1 1 1 segments on for both com1 and com2
serial data output 1. when stopped with cl at the low level 2. when stopped with cl at the high level ccb address ...................... [43h] kd1 to kd30 ...................... key data sa ...................................... sleep acknowledge data note: if key data is read when do is high, the key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. output data 1. kd1 to kd30 ..... key data when a key matrix with up to 30 keys is formed using the ks1 to ks6 output pins and the ki1 to ki5 input pins, the key data corresponding to a given key will be 1 if that key is pressed. the table below lists that correspondence. when the output pins ks1/s44 and ks2/s45 are selected for segment output by the control data k0 and k1, the key data items kd1 to kd10 will be 0. 2. sa ...................... sleep acknowledge data this output data is set according to the state when the key was pressed. if the lsi was in sleep mode, sa will be 1, and if the lsi was in normal mode, sa will be 0. sleep mode when s0 or s1 in the control data is set to 1, the oscillator at the osc pin will stop (it will restart if a key is pressed) an d the segment and common outputs will all go to the low level. this reduces the lsi power dissipation. however, the s1/p1 to s4/p4 output pins can be used as general-purpose output ports even in sleep mode if selected for such use by the p0 and p1 control data bits. no. 4828- 8 /16 lc75852e, 75852w item ki1 ki2 ki3 ki4 ki5 ks1/s44 kd1 kd2 kd3 kd4 kd5 ks2/s45 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30
key scan operation 1. key scan timing the key scan period is 375t [s]. the key scan is performed twice to reliably determine the key on/off states, and the lsi detects key data agreement. when the key data agrees, the lsi determines that a key has been pressed, and outputs a key read request (by setting do low) 800t [s] after the key scan started. if a key is pressed again without the key data agreeing, a key scan is performed once more. thus key on/off operations shorter than 800t [s] cannot be detected. * 1 the high or low states of these signals in sleep mode are determined by the s0 and s1 control data bits. 2. key scan during normal mode the pins ks1 to ks6 are set high. a key scan starts if any key is pressed, and the scan continues until all keys have been released. multiple key presses can be recognized by determining if multiple key data bits have been set. when a key has been pressed for 800t [s] (where t = 1/f osc ) or longer, a key data read request (do is set to low) is output to the controller. the controller acknowledges this request and reads the key data. however, do will go high when ce is high during a serial data transfer. after the controller has finished reading the key data, the lsi clears the key data read request (by setting do high) and performs another key scan. note that since do is an open drain output, a pull-up resistor of between 1 and 10 k is required. no. 4828- 9 /16 lc75852e, 75852w
3. key scan during sleep mode the pins ks1 to ks6 are set high or low according to the s0 and s1 control data bits. (see the description of the control data function for details.) if a key for a line corresponding to one of the pins ks1 to ks6 which is high is pressed, the oscillator at the osc pin starts and a key scan is performed. the key scan continues until all keys have been released. multiple key presses can be recognized by determining if multiple key data bits have been set. when a key has been pressed for 800t [s] (where t = 1/f osc ) or longer, a key data read request (do is set to low) is output to the controller. the controller acknowledges this request and reads the key data. however, do will go high when ce is high during a serial data transfer. after the controller has finished reading the key data, the lsi clears the key data read request (by setting do high) and performs another key scan. note that since do is an open drain output, a pull-up resistor of between 1 and 10 k is required. key scan example in sleep mode example: here s0 = 0 and s1 = 1 (this is a sleep in which only ks6 is high.) multiple key presses without the insertion of additional diodes, the lc75852 supports key scan for double key presses in general, triple key presses of keys on the lines for input pins ki1 to ki5, and multiple key presses of keys on the lines for the output pins ks1 to ks6. however, if multiple key presses in excess of these limits occur, the lc75852 may recognize keys that were not pressed as having been pressed. therefore, series diodes must be connected to each key. no. 4828- 10 /16 lc75852e, 75852w
1/2 duty - 1/2 bias lcd drive scheme res and the display controller since the lsi internal data (d1 to d90 and the control data) is undefined when power is first applied, the output pins s1/p1 to s4/p4, s5 to s43, com1, com2, ks1/s44 and ks2/s45 should be held low by setting the res pin low at the same time as power is applied. then, meaningless displays at power on can be prevented by transferring data from the controller and setting res high when that transfer has completed. figure 2 no. 4828- 11 /16 lc75852e, 75852w com1 com2 s1 to s45 outputs for segments on com1 side being lit s1 to s45 outputs for segments on com2 side being lit s1 to s45 outputs for segments on com1,com2 sides being lit s1 to s45 outputs for segments on com1,com2 sides not being lit
internal block states during the reset period (when res is low) 1. clock generator reset is applied and the basic clock stops. however, the state of the osc pin (the normal or sleep state) is determined after the control data s0 and s1 has been sent. 2. common driver, segment driver & latch reset is applied and the display is turned off. however, display data can be input to the latch. 3. key scan reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is disabled. 4. key buffer reset is applied and all the key data is set to the low level. 5. ccb interface, control register, shift register to allow serial data transfers, reset is not applied to these circuits. x: don? care note: 3. these output pins are forcibly set to the segment output mode and held low. 4. immediately following power on, these output pins are undefined until the control data s0 and s1 has been sent. 5. since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k is required. this pin is held high during the reset period even if key data is read. no. 4828- 12 /16 lc75852e, 75852w output pin state during reset s1/p1 to s4/p4 l * 3 s5 to s43 l com1, com2 l ks1/s44, ks2/s45 l * 3 ks3 to ks5 x * 4 ks6 h do h * 5 output pin states during the reset period (when res is low)
sample application circuit note: * since do is an open-drain output, a pull-up resistor is required. select a value (between 1 and 10 k ) that is appropriate for the capacitance of the external wiring so that the waveforms are not distorted. notes on controller display data transfer the lc75852 transfers the display data (d1 to d90) in two operations. to assure visual display quality, all the display data should be sent within a 30 ms or shorter period. no. 4828- 13 /16 lc75852e, 75852w
notes on controller key data read techniques 1. controller key data reading under timer control flowchart timing chart t3 .................. key scan execution time (800t [s]) when the key scan data for two key scans agrees t4 .................. key scan execution time (1600t [s]) when the key scan data for two key scans does not agree and a key scan is executed again t5 .................. key address (43h) transfer time t6 .................. key data read time t = description when determining key on/off and reading key data, the controller must confirm the state of do output when ce is low for each period t7. when do is low, the controller recognizes that a key has been pressed and reads the key data. during this operation t7 must obey the following condition: t7 > t5 + t6 + t4 if key data is read when do is high, the key data (kd1 to kd30) and the sleep acknowledge data (sa) will be invalid. 1 f osc no. 4828- 14 /16 lc75852e, 75852w
2. controller key data reading under interrupt control flowchart timing chart t3 .................. key scan execution time (800t [s]) when the key scan data for two key scans agrees t4 .................. key scan execution time (1600t [s]) when the key scan data for two key scans does not agree and a key scan is executed again t5 .................. key address (43h) transfer time t6 .................. key data read time t = 1 f osc no. 4828- 15 /16 lc75852e, 75852w
lc75852e, 75852w ps no.4828-16/16 ? description when determining key on/off and reading key data, the controller must confirm the state of do output when ce is low. when do is low, the controller recognizes that a key has been pressed and reads the key data. after the time t8, the next key on/off determination and reading key data must be confirmed by the state of do output when ce is low. during this operation t8 must obey the following condition : t8 > t4 if key data is read when do is high, the key data (kd1 to kd30) and the sleep acknowledge data (sa) will be invalid. on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner.

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